Many state-of-the-art chips are expected to perform complicated tasks, which may require portions of an integrated circuit device to have different electrical characteristics. These different portions of the integrated circuit device may be referred to as “sub-circuits,” which may require contradictory electrical characteristics, such as high voltage versus low voltage, analog (high precision) versus digital logic and/or mixed signal, low frequency versus high frequency, high immunity to noise versus relative insensitivity to noise, parasitic crosstalk and so on. A major challenge in forming integrated circuit devices is trying to combine various sub-circuits within one integrated circuit device without compromising quality of signal, functionality, size and cost.
At present, there are several methods that attempt to solve this major challenge. None of these methods are fully successful or cost effective. These methods can be generally categorized into two groups: “multi-die” solutions and “on-chip” solutions.
For “multi-die” solutions, there are presently two methods called “multi-chip-module” and “multi-package.” “Multi-chip-module” employs packaging several separate but functionally related dies, i.e., chips, into a single electrical package. The separate dies within the single electrical package are electrically connected in order to perform the combined task. This method may suffer from several serious drawbacks and may not completely answer cost, size and other challenges. This method may have a high fabrication cost due to the multiplicity of dies and a larger package, and it may increase package complexity (e.g., complicate design of each die). It may compromise performance quality since signals need to be driven across wire bonds pads versus submicron on-chip interconnects, and thus increase power dissipation, noise and reduce speed.
“Multi-package” employs packaging several separate but functionally related dies i.e.,—chips, each into separate electronic packages. All packages then must be mounted and connected on a printed circuit board (PCB) in order to perform the combined task. This method may also suffer from several serious drawbacks. First, like the “multi-die” method, the multi-package method may increase total cost of the solution and complexity. The method may degrade quality of performance even more since driving PCB wires in addition to the wire bonds pads impedes speed further and increases power dissipation and noise.
For “on-chip” solutions, there are presently two methods called “on-chip-compensation” and “grounding-and-isolation-network.” Compensation circuitry employs various specially designed electronic circuits that do not perform part of the intended task but rather attempt to compensate for the problems that occur as a result of the existence of mixed electrical characteristics on a single die. This method may suffer from serious drawbacks. The method may significantly increase design complexity and hence design cost. The method may also increase development risk due to additional new sub-circuits, and to present additional sub-circuits is only a partial solution at best.
Extensive “grounding-and-isolation-network” employs additional ground planes and power buses beyond those required for performing the task itself. This method may also suffer from serious drawbacks. It may increase die area and number of pads, and may increase package size, all of which increases total cost. The method may add additional design complexity to the chip and may increase the complexity of the external circuitry that is required to rout and supply the extra ground and power lines. This method may be only a partial solution that suffers from parasitic substrate coupling and compromises quality of performance.